GAAFETs and CFETs Emerge as Promising Solutions for Advanced IC Production New Research Reveals Revolutionary Advancements in 3D Stacking for 3 nm ICs . Credit: techxplore.com

A recent article in the National Science Review journal presents a comprehensive overview of the research conducted by Prof. Huaxiang Yin and his team from the Institute of Microelectronics of Chinese Academy of Sciences.

The team has extensively studied the evolution of Si-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) over the past two decades, encompassing advancements in theory, materials, and processes. These developments have paved the way for the production of advanced integrated circuits (ICs).

The team's analysis reveals that the traditional fin field-effect transistor (FinFET) design has been replaced by the more advanced Stacked NanoSheet and NanoWire Gate-All-Around FETs (GAAFETs) for the 3 nm node.

The review delves into the latest GAAFET integration methods and the recent progress made in research institutions and IC industries. It also highlights the key challenges faced in fabricating GAAFETs, such as achieving high-quality GeSi/Si superlattice periodic epitaxy and SD-selective epitaxial defects, reducing parasitic sub-fin channel leakage, and addressing low hole mobility and high parasitic capacitance during AC operation.

The authors also discuss several innovations in GAAFETs, including Forksheet FETs, Tree FETs, Fishbone FETs, and CombFETs. Along with GAAFETs, 3D Stacked FETs (3DS-FETs) also known as CFETs, are emerging as a promising solution for scaling towards the 1 nm node.

The review outlines two CFET integration methods - sequential and monolithic CFETs - and compares their respective advantages and fabrication challenges. Additionally, the use of new channel materials, such as CNTs, 2DMs, and AOSs with low-temperature processing capabilities, is gaining traction in the 3D stacking technology sector.

Apart from advancements in device structure and processes, CFETs also require a thorough understanding of DTCO or STCO to achieve optimal performance. This involves consideration of various factors such as transistors, circuits, and systems at different levels to maximize PPA (power, performance, and area) gain.

In addition to horizontal and lateral conductance channels, the review also explores the potential of vertical GAAFETs (VGAAFETs) and their benefits in terms of reduced contacted gate pitch, SDC, and SRAM cell areas. VGAAFETs also present new prospects for 3D integration in applications involving dynamic RAM (DRAM) and NOR-type memories.

The authors conclude by discussing the critical challenges that need to be addressed for successful implementation of vertical transistor 3D stacking in mainstream IC industries. These include precise process control at an atomic level, efficient heat dissipation, and minimizing parasitic capacitance and resistance during high-speed circuit operation.

They also provide insights into the future possibilities of integrating 3D stacking with innovative theory transistors like tunneling, negative capacitance, and quantum devices, leading to revolutionary advancements in monolithic 3D chips and systems.

Overall, the review serves as a valuable resource for the development of advanced IC manufacturing, modeling, and design for 3 nm nodes and beyond.

Steven Russell
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